Optimizing 3D near-memory AI accelerators for image signal processing workloads using trust-region Bayesian optimization

Three-dimensional (3D) integration of high-bandwidth Stacked Embedded DRAM (SEDRAM) with Systolic Arrays (SAs) enables energy-efficient, high-throughput computation for edge image signal processing. Deep neural networks (DNNs) are widely adopted in advanced image classification pipelines, serving as the computational backbone for a variety of image processing applications ranging from real-time object recognition to smart camera analytics. However, the hardware design space of such 3D integrated architectures is vast and expensive to explore manually. In this paper, we introduce an efficient design space exploration methodology based on Trust-Region Bayesian Optimization (TuRBO), tailored for high-dimensional and constraint-sensitive hardware optimization. Our approach targets image processing workloads on edge AI systems, focusing on maximizing a composite figure-of-merit balancing performance and energy efficiency. Simulation-based evaluations across DNN models demonstrate that our TuRBO framework significantly improves exploration efficiency and consistently identifies superior hardware configurations, outperforming conventional methods such as Standard Bayesian Optimization, Genetic Algorithms, and Random Search. This work provides an automated, scalable pathway to designing next-generation near-memory accelerators for efficient image signal processing at the edge.