SURVEY ON POWER-AWARE TEST SCHEDULING AND SCAN CHAIN OPTIMIZATION IN SOC TESTING

The growing complexity of System-on-Chip (SoC) designs has heightened challenges related to excessive power consumption during testing, particularly due to high switching activity in scan-based methods. Managing this power effectively is essential to avoid IR-drop, thermal hotspots, yield loss, and long-term reliability issues. This paper presents a comprehensive survey of power-aware test scheduling and scan chain optimization techniques, focusing on reducing both dynamic and static power during testing without compromising fault coverage. It reviews approaches such as time-division, session-based, and thermal-aware scheduling, alongside scan chain reordering, partitioning, multi-chain architectures, and low-transition pattern generation. Design-level techniques, including clock and power gating, and test-level strategies like X-filling, are also discussed. Recent advancements integrating machine learning, heuristic optimization, and adaptive scheduling are analyzed, highlighting their potential for efficient and reliable SoC testing. Comparative insights from literature reveal emerging trends and key challenges. The study emphasizes the importance of combining design- and test-level methods to achieve low-power, cost-effective, and high-yield SoC testing in modern semiconductor manufacturing. Future research can explore AI-driven, real-time optimization frameworks for adaptive power management in complex SoC environments