A Novel 10‐GHz CMOS Carry Generator Circuit for High‐Speed Adders

ABSTRACT The carry look‐ahead adder holds a prominent position in high‐speed adders and is recognized for its unique approach to arithmetic operations. This paper presents a new high‐speed, low‐latency, low‐power 4‐bit and 64‐bit carry generator. Digital logic gates are replaced with analog current‐comparison techniques to achieve significantly enhanced performance metrics. Using a 1.1‐V power supply, simulations in TSMC 40 nm standard CMOS technology show a 0.046‐pJ power–delay product (PDP) and a 1.3 pJ × ps energy–delay product (EDP) with a 28‐ps delay for the carry generator, a 10‐GHz maximum clock speed, and a total latency of 293 ps to generate a 64‐bit carry. The layout of the proposed carry generator occupies 4400 μm 2 of chip area. This novel method significantly enhances several critical parameters, including system complexity and the number of transistors utilized. Additionally, it substantially reduces both delay and latency, enhancing overall operational speed and system responsiveness.