Scalable Inter‐Dielectric Engineering via Vapor‐Phase Synthesis Process for Top‐Gate MoS ₂ Thin‐Film Transistor

2D semiconductors are promising channel materials for next-generation thin-film transistors (TFTs) in Internet of Things (IoT) devices. However, their inert, dangling-bond-free surfaces make uniform high-k dielectric integration challenging and can lead to interface defect formation. Here, a scalable inter-dielectric engineering strategy is introduced to address this challenge, using initiated chemical vapor deposition (iCVD) to deposit an ultrathin nonpolar poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3) film as an interlayer between MoS₂ and HfO₂. This pV3D3 buffer layer forms uniformly without pinholes or clusters on MoS₂, yielding excellent interface quality and effectively suppressing HfO₂-induced uncontrollable doping effect and trap formation in MoS₂. As a result, the MoS₂ top-gate transistors with pV3D3/HfO₂ dielectric exhibit nearly ideal switching characteristics, including a subthreshold swing (SS) of 60.9 mV dec^-1, negligible hysteresis of ≈20 mV, and low interface trap density (D_it,avg) of 8.9 × 10¹⁰ cm^-2e^-1V^-1. Furthermore, an overlapping top-gate structure design minimizes contact resistance, achieving an I_ON/I_OFF ratio above 10⁸, a field-effect mobility (µ_FE) of 19.2 cm²V^-1s^-1, and minimum subthreshold swing (SS_min) of 80.6 mV dec^-1. This iCVD based inter-dielectric method is further validated on a flexible MoS₂ top-gate transistors and logic circuits, demonstrating its potential for scalable and large-area high-performance 2D electronics.