Miti-CAT: Mitigating Power Side-Channel Vulnerabilities in FPGA-Based CNN Accelerators Through Distributed Convolution Computation

The integration of Field Programmable Gate Arrays (FPGAs) within heterogeneous systems, particularly in data centres, has significantly enhanced performance and adaptability at the system level, especially for complex tasks like image recognition. However, this advancement comes with security concerns, particularly when FPGAs are used to accelerate computations involving sensitive data, as inputs can be leaked through side-channel attacks. The study demonstrates the potential of such attacks using a Time-to-Digital Converter (TDC)–based inband control side-channel attack. In this paper, we present a novel countermeasure called Mini-CAT to protect FPGA-CNN accelerators against power-based side-channel attacks by splitting the computations in the first CNN layer. This method obscures power consumption, significantly reducing the likelihood of input data leakage. Experimental results show that the attack success rate is reduced from $71 \%$ to $37 \%$, achieving a $34 \%$ improvement in security, while maintaining a classification accuracy above $\mathbf{9 7 \%}$. Furthermore, our experiments show a latency reduction of approximately $16.7 \%$. The increased hardware overhead is acceptable, with LUT usage rising by only $1.01 \%$ due to the defence logic. Our work confirms that the proposed defence effectively mitigates these risks without compromising FPGA accelerator performance and without introducing any more redundant hardware.