Acceleration of McEliece Cryptosystem with Instruction Set Extension for RISC-V

There is an increasing need for secure PQC cryptosystems due to the progress in quantum computing technology. One of the main constraints of these systems is that they are resource intensive, and could benefit from hardware acceleration. A set of hardware accelerators have been designed for the PQC public key cryptosystem, McEliece, for encryption and decryption. These have been integrated into a RISC-V processor via an instruction set extension. The performance of the system was tested for a modification of McEliece with reduced parameters, and there was a $72 \%$ reduction in the number of cycles for encryption, and a $50 \%$ reduction for decryption. The maximum frequency of the RISC-V processor was not reduced, and the area used by the accelerators was 4,326 ALMs on a Cyclone V FPGA.