Improving Neural Network Fault Tolerance Against Weight Attack

The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters’ fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.

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Publication Details

Journal
IEEE Open Journal of Circuits and Systems
Published
2025-01-01
DOI
https://doi.org/10.1109/ojcas.2025.3602678
Primary Topic
Anomaly Detection Techniques and Applications
Type
article
Field-Weighted Citation Impact
0.00

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article

Improving Neural Network Fault Tolerance Against Weight Attack

Vanessa Chen, Ethan Chen, C. Cheng
IEEE Open Journal of Circuits and Systems
Anomaly Detection Techniques and Applications
article

Improving Neural Network Fault Tolerance Against Weight Attack

Vanessa Chen, Ethan Chen, C. Cheng
article en

Abstract

The increase of neural networks used in mission-critical applications requires protecting model parameters to maintain correct inferences. While traditional threats like adversarial inputs have been well-studied, recent research in neural network security has explored attacking model weights to degrade prediction accuracy. Many studies focused on developing fault detection methods, and few recovery strategies have been offered. This work proposes combining neural compression technique with modular redundancy to enhance model parameters’ fault tolerance against adversarial bit-flips at runtime. The fault tolerance improvement of the proposed method is demonstrated with two model architectures and two datasets. Further, a field programmable gate array realization of the scheme has been implemented to demonstrate a hardware proof of concept.

IEEE Open Journal of Circuits and SystemsVol. 6
Carnegie Mellon University (US)
National Science Foundation, Office of Naval Research, Army Research Office
Openalex Percentile: Top 88%
Anomaly Detection Techniques and Applications
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