A Ka-Band SPDT CMOS Switch With CLC-Based Matching for 5G NR Beamforming Systems

This article presents a bandwidth enhancement technique for a single-pole double-throw (SPDT) CMOS switch targeting 5G new radio (NR) applications. The switch employs a capacitor–inductor–capacitor (CLC) network in both Tx and Rx modes to maintain impedance near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\Omega $</tex-math> </inline-formula>, enabling proper matching while supporting 5G NR requirements. In the Tx mode, all transistors are turned on to reduce voltage stress from the high output power of the power amplifier (PA), thereby improving power-handling capability. The proposed design was fabricated in a 65-nm RFCMOS process and operates from 26 to 31 GHz. Measurement results show an insertion loss of less than 2.39 dB and isolation greater than 26.7 dB in the Tx mode and an insertion loss below 1.87 dB with isolation exceeding 34.1 dB in the Rx mode. Moreover, the design achieved a high Rx isolation of 34.1 dB and an input P<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 32.9 dBm in the Tx mode, underscoring its suitability for 5G NR front-end modules.