Controlling Bias Field of Pinned Layer Stacks for Double‐Pinned‐Layer Magnetic Tunnel Junction for STT‐MRAM

Abstract Double‐pinned‐layer Magnetic Tunnel Junction (Double PL MTJ) enhances spin‐transfer‐torque magneto‐resistive random‐access memory (STT‐MRAM) performance by requiring anti‐parallel magnetization between both PLs at free layer interfaces and minimizing magnetostatic bias field ( H bias ) from both PLs to enable reliable switching. In this study, a numerical method is established to accurately calculate H bias and investigate PL designs that simultaneously fulfill both conditions. Among the configurations examined, a bottom PL composed of anti‐parallel (AP) coupled three magnetic layers (FM1, FM2, and FM3) combined with a top PL consisting of two such layers (FM4 and FM5) is identified a optimal. This configuration achieved the desired anti‐parallel magnetization at FL interfaces and effectively suppressed H bias . The proposed structure enables a robust design strategy for Double PL MTJ, addressing key limitations such as high write current and paving the way for MTJ for large‐scale application in STT‐MRAM.