Modeling of Gate-Induced-Drain-Leakage Under Low Electric Field in FDSOI MOSFETs

In this study, we investigate and model gate-induced-drain-leakage (GIDL) in fully depleted silicon-on-insulator (FDSOI) MOSFETs under low electric fields. Traditional FDSOI SPICE models like BSIM-IMG and L-UTSOI mainly address GIDL through band-to-band tunneling (BTBT), which is significant at higher fields. However, with lower supply voltages, accurate modeling at lower fields is crucial. We develop a physics-based GIDL model that incorporates both BTBT and trap-assisted tunneling (TAT), the latter becoming important under low fields. Our model accounts for the influence of back-gate bias due to strong electrostatic coupling in FDSOI MOSFETs, particularly in the gate–drain overlap region. We also explore the temperature dependence of BTBT and TAT, providing insights into their behavior. Our model is developed based on calibrated Technology Computer-Aided Design (TCAD) simulations and validated across a range of device geometries, temperatures, and bias conditions using both TCAD and experimental data. Implemented in Verilog-A, our model is compatible with any industry-standard FDSOI SPICE model, providing enhanced accuracy for low-field GIDL prediction.