A Hardware-Efficient AEAD Stream Cipher Based on a Hybrid Nonlinear Feedback Register Structure

In this paper, we propose the hybrid register stream cipher, a hardware-oriented AEAD-capable stream cipher based on nonlinear feedback shift registers (NLFSRs) and Composite Mersenne Product Registers (CMPRs) designed to balance security and hardware efficiency. Our proposed stream cipher integrates a 128 -bit NLFSR with a 128 -bit CMPR, achieving highly nonlinear internal state evolution while enabling scalable and lightweight hardware implementations. The hybrid register structure supports a 128 -bit key, 96-bit initialization vector, and variable-length messages with associated data, offering 128bit security with a 64 -bit authentication tag. Statistical testing via the NIST Statistical Test Suite and bit contribution tests confirms the pseudorandomness of the output of our design. ASIC hardware implementation results demonstrate that the hybrid register stream cipher outperforms prominent lightweight stream ciphers such as TRIVIUM, Espresso, and Grain-128AEADv2 both in terms of area and energy consumption, with the hybrid register stream cipher achieving up to $25.8 \%$ lower hardware area and $67.5 \%$ lower energy consumption than the comparison candidates. Finally, we demonstrate that our hybrid register construction can be easily scaled to support different key and IV sizes.