A Study on the 4H-SiC-based ESD Protection Circuit Using Low Trigger Voltage and Gate Leakage Prevention Technology by Adding PNP BJT

In this paper, we investigate a technique that integrates a PNP bipolar junction transistor (BJT) to reduce the trigger voltage of a 4H-SiC-based Gate-Grounded NMOS (GGNMOS). The proposed ESD protection circuit lowers the trigger voltage by adding a P+ region to the conventional GGNMOS structure and prevents leakage current by connecting the gate electrode, which was previously linked to the cathode, to the PNP BJT. Through this design, the discharge operation and reliability of the 4H-SiC-based ESD protection circuit are enhanced, while the wide snapback characteristics are improved. To compare and analyze the current discharge behavior of the proposed ESD protection circuit, the electrical characteristics of the device were measured using a Transmission Line Pulse (TLP) test system. Additionally, the measurement results were analyzed based on variations in the design parameter D1(Spacing between N+ and P+ at the anode terminal), and the electrical characteristics under temperature variations were examined to verify the thermal reliability of the 4H-SiC-based ESD protection circuit.