Scalable Bit Partitioning for Hybrid Random Number Generation in Parallel Stochastic Computing

Stochastic computing (SC) allows error tolerance design and the ability to perform complex binary operations using simple digital logic circuits, advantageous for low-power design. However, it requires a longer computation time for higher accuracy. To address this, we propose a novel random number generator (RNG) that produces multiple random numbers simultaneously, reducing computation time through parallel processing while achieving lower hardware resource consumption compared to conventional parallel RNG. Our design uses fixed upper bits and a single RNG to generate multiple random numbers in parallel. This approach demonstrates computation speeds up to 64 times faster than conventional methods while reducing area and power by up to 68.2% and 81.9%, respectively, when implemented in 65-nm CMOS technology. Furthermore, we prove the efficacy of our proposed design in digital image processing applications.