Optimizing OpenCL Barrier Synchronization and Memory Efficiency on Multi-Core DSPs

Heterogeneous platforms combining CPUs and DSPs offer the potential for energy-efficient computing but are difficult to program. OpenCL enables code portability across processors but does not guarantee performance portability on DSPs due to the unique challenges in barrier synchronization and local memory management. This article introduces OctoCL , a compiler-based framework that addresses these challenges through two key optimizations: (1) a recomputation-based variable expansion technique to reduce barrier synchronization overhead, and (2) automatic merging of memory access patterns into DSP-DMA operations for efficient data transfers. We evaluate OctoCL using 18 OpenCL benchmarks from the Parboil and Rodinia suites. Experimental results show that OctoCL achieves an average speedup of 1.46× (up to 3.36×) over the baseline OpenCL compiler on the FT-M7032 CPU-DSP platform. These optimizations enhance performance portability while preserving backward compatibility, requiring no manual code modifications.