Investigation of L-shaped split-gate eFlash memory with enhanced gate coupling in a 55 nm node
As data processing demands increase, embedded flash is advancing toward low power consumption, low manufacturing cost, and high operation speed, as well as large memory windows (MW). A self-aligned split-gate floating-gate (FG) NOR-type flash memory cell and array have been proposed under a 55 nm node. Low-voltage erase and high-speed program operation have been achieved owing to a low EP-to-FG coupling ratio of 0.09 and a high CG-to-FG coupling ratio of 0.67, respectively. Moreover, up to 8 masks can be reduced in our low-cost process, as compared to that of the third-generation SuperFlash. Additionally, close to 5-bit states have been realized in the large MW of 7.1 V in a single-bit cell, which is mostly attributed to the threshold voltage (Vth) tuning by drain-side dual-pocket implantation.
Authors
- Q. J. Xu (ORCID: https://orcid.org/0009-0002-5500-9566)
- Kun Ren (ORCID: https://orcid.org/0000-0002-2983-168X)
- Wei-an Ling
- Dawei Gao (ORCID: https://orcid.org/0009-0002-7786-1506)
- Dianyu Qi (ORCID: https://orcid.org/0000-0003-2912-9388)
- Yongyu Wu
- Guangji Li (ORCID: https://orcid.org/0000-0002-0102-5088)
- Chia-Lung Tsai (ORCID: https://orcid.org/0000-0002-2739-6952)
- Zhenghui Xia (ORCID: https://orcid.org/0000-0002-5895-7329)
- Miao Zhou (ORCID: https://orcid.org/0009-0005-1085-8742)
- Xuan Li (ORCID: https://orcid.org/0000-0001-6737-5892)
- Isaac L. Chuang
- D.-T. Fan
- T.H. Cheng
Institutions
- ON Semiconductor (United States) (US)
- Taipei City University of Science and Technology (TW)
- Zhejiang Lab (CN)
- Zhejiang University of Technology (CN)
- Zhejiang University (CN)
Publication Details
- Journal
- Applied Physics Letters
- Published
- 2025-08-25
- DOI
- https://doi.org/10.1063/5.0266252
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73
Funders
- National Key Research and Development Program of China