On Improving the Performance of Intra- and Inter-chiplet Interconnection Networks in Multi-chiplet Systems for Accelerating FHE Encrypted Neural Network Applications
Fully Homomorphic Encryption (FHE) is regarded as a promising way to protect data privacy with encrypted computation. Due to high computation overhead, hardware based FHE accelerators were proposed to speed up FHE applications. To support complicated FHE-encrypted neural network applications, multi-chiplet based FHE accelerators were further proposed for scaling up system size, whereas one of the challenges is designing efficient intra- and inter-chiplet interconnection networks to accelerate data transfer. Conventional regular topologies like mesh or Kite either lead to high inter-chiplet transmission latency or excessive power consumption as these topologies assume uniform bandwidth or radix for nodes/links, ignoring the highly irregular distribution of inter-chiplet communication volumes. On the other hand, the problem of generating customized intra- and inter-chiplet interconnection networks has high complexity and previous network-on-chip topology generation works cannot efficiently improve the performance of intra- and inter-chiplet interconnection networks. In this article, the intra- and inter-chiplet interconnection optimization problem is defined, aiming to minimize the execution time of FHE applications under cost and power constraints. To efficiently solve this problem, we propose a bilevel optimization algorithm, which decomposes the problem into three sub-problems: (1) FHE parameters selection, (2) task-to-core mapping, and (3) intra-/inter-chiplet interconnection network topology generation. These sub-problems are then solved iteratively. Experimental results demonstrate that our proposed method reduces execution time by 51.66%, 43.16%, 39.44%, 43.34%, and 27.70% compared with REED and four multi-chiplet based FHE accelerators with mesh, Kite, Butterfly, and Florets as inter-chiplet interconnection networks. Therefore, the proposed method can effectively accelerate FHE applications on large-scale multi-chiplet systems.
Authors
- Kui Ren (ORCID: https://orcid.org/0000-0003-3441-6277)
- Jinhui Ye
- Mei Yang (ORCID: https://orcid.org/0000-0002-9510-1079)
- Xiaohang Wang (ORCID: https://orcid.org/0000-0002-2263-5643)
- Zheang Fu
- Amit Kumar Singh (ORCID: https://orcid.org/0000-0003-2056-0569)
- Sihai Qiu (ORCID: https://orcid.org/0000-0002-5619-8226)
- Yingtao Jiang (ORCID: https://orcid.org/0000-0001-7453-9365)
- Jie Song
- Xin Tang
- Mingzhe Zhang (ORCID: https://orcid.org/0000-0002-6440-7550)
- Xiaodong Li
- Zonghao Lai (ORCID: https://orcid.org/0009-0004-0539-2821)
Institutions
- University of Essex (GB)
- University of Nevada, Las Vegas (US)
- Beijing Microelectronics Technology Institute (CN)
- Antea Group (France) (FR)
- Shine Micro (United States) (US)
- Institute of Zoology of the Slovak Academy of Sciences (SK)
- Zhejiang University (CN)
Publication Details
- Journal
- ACM Transactions on Embedded Computing Systems
- Published
- 2025-08-25
- DOI
- https://doi.org/10.1145/3762995
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Ant Group
- National Natural Science Foundation of China
- National Key Research and Development Program of China