Cumulative-Time Signal Temporal Logic

Signal Temporal Logic (STL) is a widely adopted specification language for Cyber-Physical Systems that can be used to express critical temporal requirements, such as system safety and response time. STL’s expressivity, however, is not sufficient to capture the cumulative duration during which a property holds within an interval of time. To overcome this limitation, we introduce Cumulative-Time Signal Temporal Logic (CT-STL) which operates over discrete-time signals and extends STL with a new cumulative-time operator. This operator compares the sum of all timesteps for which its nested formula is true with a threshold. We present both a qualitative and a quantitative (robustness) semantics for CT-STL and prove the soundness and completeness of the robustness semantics. We also provide an efficient online monitoring algorithm for both semantics. We demonstrate the utility of CT-STL via two case studies: specifying and monitoring cumulative temporal requirements for a microgrid and an artificial pancreas.

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Publication Details

Journal
ACM Transactions on Embedded Computing Systems
Published
2025-08-25
DOI
https://doi.org/10.1145/3763237
Citations
1
Primary Topic
Formal Methods in Verification
Type
article
Field-Weighted Citation Impact
1.50

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article

Cumulative-Time Signal Temporal Logic

Shan Lin, Scott D. Stoller, Scott A. Smolka, Ezio Bartocci et al.
1 citations
ACM Transactions on Embedded Computing Systems
Formal Methods in Verification
1.50
article

Cumulative-Time Signal Temporal Logic

Shan Lin, Scott D. Stoller, Scott A. Smolka, Ezio Bartocci, Z. Zhang, Shouvik Roy, Hongkai Chen
article en
1 citations

Abstract

Signal Temporal Logic (STL) is a widely adopted specification language for Cyber-Physical Systems that can be used to express critical temporal requirements, such as system safety and response time. STL’s expressivity, however, is not sufficient to capture the cumulative duration during which a property holds within an interval of time. To overcome this limitation, we introduce Cumulative-Time Signal Temporal Logic (CT-STL) which operates over discrete-time signals and extends STL with a new cumulative-time operator. This operator compares the sum of all timesteps for which its nested formula is true with a threshold. We present both a qualitative and a quantitative (robustness) semantics for CT-STL and prove the soundness and completeness of the robustness semantics. We also provide an efficient online monitoring algorithm for both semantics. We demonstrate the utility of CT-STL via two case studies: specifying and monitoring cumulative temporal requirements for a microgrid and an artificial pancreas.

ACM Transactions on Embedded Computing SystemsVol. 24(5s)
TU Wien (AT), Chinese University of Hong Kong (HK), Illinois Institute of Technology (US), Stony Brook University (US)
National Science Foundation, Vienna Science and Technology Fund
Openalex Percentile: Top 14%
Formal Methods in Verification
1.50
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Cumulative-Time Signal Temporal Logic — Shan Lin, Scott D. Stoller, et al. · ACM Transactions on Embedded Computing Systems (2025) | TGRS Research Map | TGRS