A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer

The cascaded solid-state transformer (SST) has garnered significant attention in recent years due to its modular advantages, offering improved scalability, efficiency, and fault-tolerant capabilities. However, the modeling of N-module cascaded SSTs and their impedance characteristics remains insufficiently explored, which could hinder the reliable integration of SSTs. To address this issue, this paper proposes a matrix-based modeling method to characterize the N-module SST and establish its corresponding impedance model. A universal module equivalent block diagram, accounting for arbitrary-order harmonic disturbances, is constructed through an initial matrix aggregation. Building upon this, a second matrix aggregation is performed to develop a system-wide equivalent block diagram, which accommodates any combination of modules, thus enabling standardized representation and modular expansion of the N-module SST. Based on the system equivalent block diagram, a transfer-matrix-based method is used to flexibly compute the SST impedance expression. Using the derived impedance model, the impact of factors such as module differences, operating conditions, and hardware parameters on port impedance is discussed. The influence of these factors on overall system stability is also discussed. Finally, the accuracy and validity of the impedance model, along with the related stability analysis, are verified through a hardware-in-the-loop (HIL) experimental setup.