Design for Slew-Rate in Multi-Stage CMOS OTAs

Cascading gain stages in CMOS Operational Transconductance Amplifiers (OTAs) has become a necessity in applications with high gain requirements, where the contribution of each stage to the overall gain is well-known and carefully designed. Many of these applications also impose requirements on speed, including a minimum Slew-Rate (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i>) to ensure signal fidelity, however the impact of individual gain stages on the overall <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i> in multi-stage OTAs has been difficult to characterize–let alone carefully design. The difficulty arises due to the complexity of the compensation networks involved in these OTAs. This paper presents a systematic design approach for achieving a target <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i> in multi-stage CMOS OTAs, enabled through the utility of a novel analytical model for estimating the lower-bound Slew-Rate in multi-stage OTAs. The model evaluates individual currents and equivalent capacitances at the output node of each stage, providing insights on the dominant node slowing down the overall <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i>. For generality, the model establishes the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i> analysis based on N-stage designs, and considers widely employed compensation networks. Example designs, with post-layout simulations and measurements of a 3- and a 4-stage CMOS OTA, and with post-layout simulations of a 5-stage CMOS OTA, are presented for validating the model’s utility. The results show strong agreement between theoretical, simulated, and measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i> values, confirming the model’s reliability in estimating the lower-bound <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i>, and its utility in a systematic design-for-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SR</i> approach in multi-stage CMOS OTAs.