Nonvolatile Double- and Triple-Node-Upset Tolerant Latch Designs Based on FeFET and CMOS

Nonvolatile memories (NVMs) are widely used in energy-harvesting Internet of Things systems, and ferroelectric field-effect transistor (FeFET) devices present opportunities for NVM designs due to such important features as low power consumption, fast access speed, and compatibility with the CMOS technology. However, rising soft error rates caused by radiation pose a severe reliability challenge, and state-of-the-art radiation hardening by design methods are urgently needed. This article presents a nonvolatile double-node-upset-tolerant latch (NVDTL) and its enhanced version, i.e., a nonvolatile triple-node-upset (TNU)-tolerant latch (NVTTL), which do not require auxiliary control signals to provide the nonvolatility feature. The NVDTL utilizes two parallel single-node-upset recovery units. Each unit integrates multiple two-input <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i>-elements and input-split inverters with embedded FeFETs to form interlocked feedback loops. Moreover, the NVTTL enhances its robustness reliability through a two-stage error-blocking mechanism in the output module to provide TNU tolerance. Simulation results based on Cadence Virtuoso have validated the proposed latches’ fault tolerance and nonvolatility and also show that the comprehensive delay–power–area product is reduced by approximately 77.21% for the NVDTL and 61.67% for the NVTTL, and the power–delay product is reduced by 23.45% and 11.15%, respectively, compared to the existing latches with the same level of radiation hardness.