A NS-SAR Assisted CT Incremental ADC With Input Signal Track-and-Reset for Extending Maximum Stable Amplitude

Incremental analog-to-digital converters (IADCs) are well-suited for multiplexing across sensor nodes. Continuous-time (CT) implementations often offer better energy efficiency than switched-capacitor circuits. This paper presents a medium-bandwidth and high-resolution IADC incorporating a second-order CT loop filter and an entirely passive noise-shaping successive approximation-register (SAR) internal quantizer with a direct input feedforward path. The noise-shaping SAR quantizer enhances noise shaping by one additional order. Meanwhile, the direct input feedforward path mitigates the voltage ringing issues that arise when resetting the loop filter during incremental operation, thereby successfully extending the maximum stable amplitude. The proposed hardware prototype is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu $</tex-math> </inline-formula>m CMOS technology, occupying an active area of 0.38 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. It achieves a peak SNDR of 89.2 dB with an input amplitude of -2 dBFS and a DR of 91.9 dB for 100 kHz signal bandwidth. Operating at a 1.8V supply voltage, the prototype consumes 1.19 mW, resulting in a Schreier FoM of 168.4/171.1 dB.