Multi-Chiplet Implementation of a TOPS-Ready Hyperdimensional AWGR-Based Photonic Tensor Core

The exploding scale and as such energy and computational power requirements of emerging Deep Learning (DL) models, has fueled the quest for analog computational platforms capable of surpassing the energy efficiency and compute power limitations of currently deployed digital implementations [1]. In this context, Photonic Neural Networks (PNN) have arisen as a powerful candidate capable of harnessing light's low-propagation losses and multiple computational axes i.e. spatial, wavelength and time, towards delivering Tera Operations per second (TOPS) operations at fJ/OP energy efficiencies [2]. The lack, however, of a PNN architecture that optimally synergizes light's multiplexing computational axes, has restricted PNN TOPS scale demonstrations to diffractive optics-based systems [3], with their limited reconfigurability hindering their deployment as practical solutions for adaptable computing environments. The 100 TOPS barrier was only recently breached [4], through the use of a multi-dimensional arrayed waveguide grating router (AWGR)-based architecture that simultaneous uses time-, wavelength- and space- division multiplexing (T-W-SDM). Harnessing, however, the significant compute power performance metrics achieved by the proposed AWGR-based layouts, necessitates an integration roadmap capable of (a) Leveraging the best-in-class silicon photonic (SiPho) technologies in a modulator multi-chiplet approach, towards footprint and energy efficient layouts (b) Re-use of the existing SiPho interconnect developments for rapid-deployment and low-cost integration.