Memristor-Assisted Secure SRAM Architectures for Protection Against Data Imprinting Attacks

In this work, we investigate the vulnerability of Static Random Access Memory (SRAM) to data imprinting attacks and propose a secure bit-cell architecture that integrates memristor-based control for conditional data toggling. The design extends the conventional 6T SRAM by incorporating a memristor-assisted path capable of performing XOR operations, thereby enabling in-situ logic and enhanced security. The proposed bit-cell simultaneously supports three key functionalities: logical implication (NOT), XOR-based computation, and secure data toggling. Additionally, we extend this architecture to an array-level configuration that enables simultaneous toggling of multiple bits within a single clock cycle. This array-wide control significantly improves resistance to data imprinting while maintaining computational efficiency. The design was implemented using 22nm GF FD-SOI technology with TiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>-based memristor models. Extensive simulations confirm the functional correctness and robustness of the proposed architecture under various attack scenarios. The results demonstrate that the design offers strong protection against data imprinting with minimal impact on speed and power, making it a promising solution for secure memory in cryptographic and AIoT systems.