Transmission Analysis and Space-Efficient Structuring of Triangular TSVs for Dense Integration

The increasing research efforts in 3D ICs and chiplet technology, driven by the limitations of traditional scaling and the slowdown of Moore’s Law, have established Through-Silicon Vias (TSVs) as a pivotal component in VLSI design. In this paper, we design triangular TSVs for space-efficient structuring to enhance integration density and conduct transmission and cross-talk analysis. The key objective of this work is to leverage the offset hexagram arrangement of triangles in TSVs to enhance area efficiency, making it suitable for smaller technology nodes. Furthermore, transmission and crosstalk analysis are performed to demonstrate its capability in ultra-wideband and efficient chip-to-chip communication. For 10 TSVs arranged in a row, the triangular offset hexagram pattern occupies 31.96% less area compared to cylindrical and square TSVs, and the area reduction will improve further as the number of TSVs in a row increases. Moreover, the architecture exhibits a –10 dB S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf> bandwidth from 0.01 to 55.51 GHz and demonstrates negligible crosstalk between ports. In addition, we evaluate performance under variations in side length, dielectric thickness, height, and edge distance to ensure a rigorous analysis. Collectively, triangular TSVs show strong potential to remarkably enhance interconnect density while maintaining excellent transmission performance, positioning them as promising candidates for next-generation 3D ICs.