A Dual-Read SOT-MRAM Bitcell Architecture for Robust In-Memory Computing

Spin-Orbit Torque Magnetoresistive RAM (SOT-MRAM) offers several advantages over traditional SRAM for in-memory computing (IMC), including non-volatility and lower leakage power. However, conventional SOT-MRAM-based IMC architectures suffer from reduced read margins due to the accumulation of bitcell output charges on shared bitlines during logic operations, which degrades robustness and sensing accuracy. In this work, we propose a novel 2T-1R SOT-MRAM bitcell architecture featuring a dual-transistor per write-path topology, enabling independent and simultaneous reads from two separate bitcells, each with its own peripheral sense amplifier. This dual-read approach significantly enhances the sense margin and reduces cross-talk compared to conventional architectures that rely on shared read paths. Furthermore, the proposed design enables robust in-memory Boolean operations—such as NAND, NOR, and XOR—positioning it as a promising solution for reliable IMC systems.