An Arbitrary Kernel Size Applicable Universal Flexible-Oriented Network on Chip (UFONoC) Neural Network Accelerator with AXI4-stream Data Transmission Protocol

In recent years, the hardware accelerator for Deep Neuron Network (DNN) has attracted attention due to the increased demand for real-time data processing in Artificial intelligence of things (AIoT) applications. With the development of various DNN architectures, the flexible architecture of neural network accelerator design has become more important. This work introduces a highly adaptable DNN accelerator design called Universal Flexible-Oriented Network on Chip (UFONoC). The UFONoC employs a kernel-based weight-wise Neural Network (NN) processing mechanism that can support any size and shape of convolution kernel or feature map in the target DNNs, resulting in greater flexibility. The UFONoC utilizes a hybrid data reuse method for packet transmission in the NoC to reduce memory access. In addition, it adopts the AXI4-stream protocol for data transmission in NoC architecture to minimize data transmission latency. Compared with the prior works, our proposed UFONoC achieves energy savings by 60% to 93% and improves hardware efficiency by 23% to 742%. Finally, we integrate the UFONoC into an AMD PYNQ-ZU to demonstrate a real industry application and reach a 94.3% accuracy.