PRISM: Toward Energy-Efficient AIoT with Processing-In-Sensor+Memory in Battery-Free Devices

The proliferation of battery-free devices for Artificial Intelligence of Things (AIoT) has been fueled by recent advances in energy-harvesting technologies and ultra-low-power systems. These devices, referred to as Intermittently Powered Systems (IPS), operate exclusively on harvested ambient energy, making them inherently susceptible to frequent power losses and execution interruptions. Despite these constraints, emerging AIoT use cases—such as automatic license plate recognition for access control and poaching deterrence, or vision-based traffic infrastructure analysis—demand real-time digit or character classification directly at the sensor node, necessitating on-device intelligence. This, in turn, requires the deployment of Artificial Intelligence (AI) workloads under severe energy and computational constraints. However, executing AI workloads on IPS remains challenging due to their intermittent energy supply, low compute throughput, and the overhead of frequent checkpointing. Binary Neural Networks (BNNs), with their reduced precision and computational complexity, offer a promising path forward for AI on resource-constrained platforms. Nevertheless, executing BNNs on traditional microcontroller (MCU)-based IPS remains inefficient due to high memory and energy overheads. Processing-in-Memory (PiM) architectures alleviate some of these inefficiencies by reducing memory access costs, yet PiM-only systems still fail to meet the stringent energy-performance envelope required by practical IPS deployments. To bridge this gap, we propose PRISM, the first architecture to jointly integrate Processing-in-Sensor (PiS) and PiM modules for executing BNN workloads efficiently on IPS platforms. PRISM computes the first BNN layer directly near the sensor array to minimize data movement and checkpointing, while leveraging PiM for deeper layers of the network. To evaluate PRISM’s energy and performance characteristics, we develop EPCEN-P, a full-stack simulation framework that models IPS-specific compute, memory, and sensor operations. Evaluations on MLP-based handwriting recognition tasks (MNIST and EMNIST) across different supply capacitance values (0.1µF, 1µF, and 10µF) demonstrate that on average PRISM achieves a 110.66× improvement in forward progress, a 110.45× reduction in checkpointing frequency, and a 145.22× reduction in execution cycles compared to an MCU-only baseline. Relative to an MCU+PiM system, PRISM achieves a 1.60× increase in forward progress, a 1.60× reduction in checkpointing events, and a 1.54× reduction in execution cycles. The EPCEN-P framework is available at this link.