Study on dislocation propagation in 300-mm Si wafer during a high thermal budget process

An experimental method was developed to investigate the relationship between dislocation propagation and temperature distribution in a 300-mm Si wafer during high thermal budget processes. Thermal budget processes such as oxidation and diffusion in Si insulated gate bipolar transistors (Si-IGBTs) fabrication can induce thermal stress due to temperature nonuniformity in wafers, potentially leading to dislocation propagation. This phenomenon may degrade both the wafer crystal quality and device performance. Therefore, it is important to suppress dislocation propagation in Si wafers during high thermal budget processes. In this study, we conducted N2 annealing experiments using a rapid thermal annealing furnace, which can create temperature distributions in wafers. In addition, we proposed a 300-mm wafer model for analyzing the temperature, stress and dislocation density. The calculated dislocation density distribution strongly agrees with the slip dislocations measured via X-ray topography, confirming that higher radial temperature gradients result in more dislocation propagation at higher temperatures. Furthermore, significant dislocation propagation causes lifetime degradation in Si wafers. • A new experimental method enables the study of dislocation propagation in 300-mm wafers. • A simulation model reveals temperature distribution, stress, and dislocation behavior in wafers. • Understanding dislocation propagation mechanisms enables strategies for dislocation suppression. • Lifetime degradation is linked to the dislocation propagation. • Proposed parameter “ f ” enables predictive estimation of dislocation behavior in complex device structures.