Comparative evaluation of robust low-power SRAM architectures

Abstract As Internet-of-Things (IoT) devices proliferate, their reliance on energy-efficient and reliable embedded memory grows exponentially. Static random-access memory (SRAM) remains a cornerstone of modern system-on-chips, yet traditional 6T cells struggle with scalability, exhibiting read/write failures at reduced voltages and nanometer-scale process nodes. To overcome these limitations, novel SRAM architecture has emerged, prioritizing robustness, power efficiency, and performance without compromising the silicon area. This work conducts a rigorous comparative study of advanced SRAM topologies in 16-nm CMOS technology, evaluating their resilience under process, voltage, and temperature fluctuations. The Schmitt-trigger-based 11T (ST11T) cell enhances data retention and read margins by a factor of 1.18, leveraging feedback-stabilized inverters and an isolated read pathway. In contrast, the differential 10T (known as ST2) variant improves writability by 3% through its dual-ended access scheme. While the low leakage 8T (LP8T) design cuts read latency by 8% and standby power by nearly an order of magnitude, its hold stability proves inferior due to disabled tail transistors in idle mode. The baseline 6T cell retains advantages in write speed and area efficiency, whereas the single-ended WRE8T topology reduces active power consumption by 55% through simplified signaling. Overall, the differential- V GND 10T (Dvgnd10T) cell emerges as the most promising candidate based on a figure-of-merit (FoM) analysis, making it well-suited for IoT-enabled portable devices. The findings of this study provide valuable insights into SRAM designers to benchmark future designs.