Modeling DRAM Access Based on Efficient Tiling in CNN Hardware Accelerators

Artificial neural networks are a subset of machine learning inspired by the biological neural networks of the human brain.These networks are applied in various fields, including natural language processing, pattern recognition and image processing.CNNs are an example of networks that have a layered structure.Due to the high volume of computations in CNNs, there is an increased need for bandwidth and memory transfers.researches have shown that the energy consumption and access time of external memory are 200x and 10x greater than internal memory.One of the main solutions to reduce energy consumption is to increase data reuse and reduce the number of accesses to external memory.Maximizing data usage reduces the number of data movements and memory accesses.One method for data reuse is loop-level scheduling and tiling.This paper models the relationship between the number of accesses to external memory when using tiling.That presented as a mathematical formula that can determine the exact number of DRAM accesses based on network parameters and the tile size.Then optimal parameters are obtained with the goal of minimizing the use of external memory and establishing the relationship between network configuration parameters and tile size.