Design of a DDR Controller Performance Test Platform Based on FPGA and SD Card
This paper proposes a DDR controller performance test platform based on FPGA and SD card. The platform utilizes the SD card as a storage medium to store the test stimuli, providing a flexible and convenient tool for the performance analysis and optimization of the DDR controller. The experimental results show that the designed test platform can accurately and effectively evaluate the performance of the DDR controller, and the test results can provide a valuable reference basis for the optimization and improvement of the DDR controller.
Authors
- Jie Zou (ORCID: https://orcid.org/0000-0001-9155-7186)
- Wang Peng (ORCID: https://orcid.org/0000-0003-3393-4208)
- Xueming Hua (ORCID: https://orcid.org/0000-0002-8416-738X)
Institutions
- Shanghai University of Engineering Science (CN)
Publication Details
- Published
- 2024-12-06
- DOI
- https://doi.org/10.1109/iaecst64597.2024.11117705
- Primary Topic
- Embedded Systems and FPGA Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00