Low Voltage Schmitt Trigger 4:1 Multiplexer Design for Portable Devices with Enhanced Performance

The multiplexer circuits using CMOS logic degrades <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{ON}} / \mathrm{I}_{\text{OFF}}$</tex> and noise immunity at low supply voltages. In this paper, two variations of the Schmitt trigger (ST) are provided for the designing of a Schmitt trigger <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4: 1$</tex> multiplexer with excellent noise immunity and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text {ON }} / \mathrm{I}_{\text {OFF }}$</tex>. Dynamic threshold MOS (DTMOS) and variable threshold CMOS (VTCMOS) ST are the key components of the two ST <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4: 1$</tex> multiplexer variants. In the LT spice simulator, 45 nm PTM technology parameters are used to analyze the performance of the proposed ST 4:1 multiplexers in terms of hysteresis width, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{ON}} / \mathrm{I}_{\text{OFF}}$</tex>, delay, and switching current. The VTCMOS ST 4:1 multiplexer has higher noise immunity due to its 64 % increase in hysteresis width when compared to the DTMOS ST 4:1 multiplexer. All multiplexers together, the DTMOS ST 4:1 multiplexer has the highest <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text {ON }} / \mathrm{I}_{\text {OFF }}$</tex> ratio. It is also noticed that the CMOS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4: 1$</tex> multiplexer has the lowest switching current with negligible hysteresis width while the VTCMOS ST 4:1 multiplexer lowers the switching current by 58% than the DTMOS ST 4:1 multiplexer which resulted in a decrease in power consumption of the circuit. Moreover, the proposed ST 4:1 multiplexers increase the speed of the circuit over the CMOS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4: 1$</tex> multiplexer. The same performance trend is confirmed through process variation at different corners. Therefore, the proposed VTCMOS ST 4:1 multiplexer is suitable for improved noised immunity and reduced power consumption whereas DTMOS ST 4:1 multiplexer is good for enhanced <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text {ON }} / \mathrm{I}_{\text {OFF }}$</tex>.