High Bandwidth and Low Latency Direct Memory Access System Design for Big Data Transmission

With the rapid growth of applications such as big data, cloud computing, and artificial intelligence, bandwidth and latency in data transmission have become critical factors, with Direct Memory Access (DMA) playing a key role. To address the current demand for high-bandwidth, low-latency data transmission, this paper designs a simple and efficient DMA system, termed Streamlined Direct Memory Access (SDMA). SDMA directly issues descriptors to user logic through a bypass interface; it implements a multi-queue mechanism to handle different data streams simultaneously, with each queue corresponding to an independent data transfer channel. By designing an event management mechanism, the system supports Message Signaled Interrupts extended (MSI-X), enabling realtime interaction between the host and application, improving system throughput and reducing system latency. The SDMA system designed in this paper was prototyped on an FPGA, and experimental results show that the transmission rate reaches 90 Gbps, with an average latency of approximately 3 microseconds.