Design and Implementation of a 100G Ethernet TCP/IP Protocol Stack Offload Engine
With the widespread application of technologies such as cloud computing, big data, and the Internet of Things, network bandwidth has been growing at a rate of 2 to 3 times per year. Currently, 10G networks have been widely adopted across various fields, while <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40 \mathrm{G} / 100 \mathrm{G}$</tex> and even 400G networks are being increasingly used in data centers and other critical areas with high traffic demands. To address issues such as processor resource overload and network latency caused by TCP/IP network protocol processing in large-scale Ethernet transmissions, this paper proposes a design method for a 100G Ethernet TCP/IP offload engine [1]. The proposed engine adopts a pipelined architecture that separates the data transmission and reception channels. Additionally, a large data block fragmentation transmission mechanism is designed, supporting TCP/IP packet checksum offloading to effectively reduce the latency and processor resource consumption during large data block transmissions. Experimental results demonstrate that the 100G Ethernet TCP/IP offload engine efficiently handles network communication protocols under high-concurrency scenarios, maintains a stable network communication bandwidth, achieves a data packet transmission rate of 37 Gbps, and keeps the average latency at the microsecond level, around 200 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu$</tex>s.
Authors
- Liguo Zhang
- Zhen Wang (ORCID: https://orcid.org/0009-0001-4113-0528)
Institutions
- Xi’an University of Posts and Telecommunications (CN)
Publication Details
- Published
- 2024-12-06
- DOI
- https://doi.org/10.1109/iaecst64597.2024.11117880
- Primary Topic
- Embedded Systems and FPGA Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00