Challenges in FPGA Implementations of Cryptographic Algorithms: a Case Study of Evolution in BLAKE Hash Functions

Hash functions today are ubiquitous in nearly all kinds of cryptographic applications. They can be found at the core of digital fingerprinting or watermarking and even in block or stream ciphers. As such, their efficient implementation not only in software but also in hardware is essential for secure and reliable functioning of virtually all contemporary complex IT systems. This paper analyses challenges which arise in realization of the three evolutionary versions of the BLAKE algorithm – which started as one of the strongest contenders in the SHA-3 competition – in configurable Field Programmable Logic Arrays (FPGA). In particular, it concentrates on (sometimes subtle) modifications introduced in the second and the third version of the algorithm and examine their impact on operation of the hardware. The analysis identifies specific peculiarities of BLAKE processing which are especially troublesome for FPGA resources and lead to excessive size and power consumption. The study starts from the standard iterative organization of cipher operation and extends with application of loop unrolling and pipelining aimed at increasing processing speed. All proposed architectures are implemented in popular Spartan FPGA devices from AMD (Xilinx) and analysed with regard to their size, speed and power consumption.