Design of Low Power Low Offset Dynamic Comparator

In this study, a low-power, low-offset dynamic comparator has been developed utilizing the DBH <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18 \mu \mathrm{m}$</tex> BCD process. The circuit implements charge multiplexing through the incorporation of a tail capacitor, which effectively reduces the average power consumption of the comparator. Following the calculation of the offset, the input pairs of the latch circuit in the conventional double-tail dynamic comparator are eliminated, thereby optimizing the offset performance of the comparator. Operating under a power supply voltage of 1.8V and a clock frequency of 10MHz, the average power consumption of the proposed comparator is approximately <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.1 \mu \mathrm{W}$</tex>. The equivalent input offset voltage, determined through 200 Monte Carlo simulations, is approximately 1.16mV.