A High-Transient, Capacitor-Free Low Dropout Regulator Based on FVF Structure

This paper presents a Capacitor-free low dropout linear regulator (LDO) based on the flipped voltage follower (FVF) structure. The FVF structure, derived from the source follower, is widely used in LDOs due to its fast feedback loop, high slew rate, and low output impedance. Employing voltage peak detection technology to realize dynamic current biasing, this design improves the load transient response of the LDO circuit without significantly increasing static power consumption. Simulation results based on the SMIC 40 nm process show that the static current of this LDO is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${39} \boldsymbol{\mu} \mathrm{A}$</tex>, with an input voltage range of 2–3.3 V and an output voltage of 1.8 V. When the load current alternates between <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100 \mu \mathrm{A}$</tex> and 10 mA within 1 ns, the output voltage undershoot and overshoot recovery times are 101 ns and 263 ns, respectively, with undershoot and overshoot amplitudes of approximately 164 mV and 143 mV. At low frequencies, the power supply rejection ratio (PSRR) reaches -44 dB under heavy loads and -50 dB under light loads.