A Continuous Model for Ferroelectric-FETs for Computing in Memory

In this work, we propose a simulation model for ferroelectric field-effect transistors (FeFETs) tailored for the design of in-memory computing circuits. For the design and simulation of in-memory computing circuits, it is crucial to consider the macroscopic behavior of FeFETs. Our proposed model not only conforms to the actual performance of FeFETs but also employs an asymptotic model to constrain the upper and lower limits of polarization in FeFETs. Furthermore, we have fitted a nonlinear function to represent the dynamic polarization change rates during different polarization transition processes. This enables our model to simulate FeFET circuits capable of continuous writing, erasing, and reading, as well as to assess the stability performance of FeFETs in in-memory computing arrays. Concurrently, we have validated a 2×2 FeFET in-memory computing array. By employing the proposed simulation model, we conducted circuit analysis and derived the correlation between the write voltage, write success rate, and crosstalk.