Low-Latency Level Switching Circuit Based on Self-Acceleration Functionality

In order to solve the problem of delay between input and output signals in a level switching circuit, a two-channel low delay level switching circuit is designed in this paper. By using a new type of acceleration module, the switching speed is improved. This circuit has a unique current generation scheme, which can accelerate the rise of the output signal by detecting the logic level of the input signal. At the same time, the self-accelerating module can generate a working current only when the input signal is a rising or falling edge so as to achieve a low power consumption design. The circuit is designed based on the 180 nm standard process of ShangHua. The delay time of the proposed circuit is about 1.6 ns, the current of the current mirror is about 600 uA, the delay time is about 25 % of the traditional dual-channel level switching circuit, and the current is about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 3 \%}$</tex>.