Improvement of Electrical Properties of HfO<sub>2</sub>/Si<sub>0.73</sub>Ge<sub>0.27</sub> Gate Stacks Through Selective Remote GeO<sub>x</sub> Scavenging
In this article, a selective remote GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> scavenging method is presented to reduce interface trap density (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub>) in HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>/Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.73</roman></sub>Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.27</roman></sub> gate stacks using an Al-rich Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>x</roman></sub> O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>y</roman></sub> cap as the scavenging layer. The GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> scavenging process is driven by the formation energy gain between Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>3</roman></sub> and GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> during postdeposition annealing (PDA). The Ni/HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>/Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.73</roman></sub> Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.27</roman></sub> metal-oxide semiconductor (MOS) capacitors subjected to the selective remote GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> scavenging method demonstrate significant reductions in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub>. Through the optimization of cap thickness and PDA temperature, a GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>-free interfacial layer (IL) in the HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>/Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.73</roman></sub> Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.27</roman></sub> gate-stack has been successfully achieved. Notably, the Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.73</roman></sub> Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.27</roman></sub> device with GeO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>-free IL could achieve an excellent <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>it</roman></sub> value of 1.3 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>11</roman></sup> eV<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>1</roman></sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>2</roman></sup>.
Authors
- Zhengyang Chen (ORCID: https://orcid.org/0009-0004-7340-4150)
- Tomonori Nishimura (ORCID: https://orcid.org/0000-0002-8000-5164)
- Choonghyun Lee (ORCID: https://orcid.org/0000-0001-9696-2308)
- Yi Zhao (ORCID: https://orcid.org/0000-0001-5368-3595)
- Yiran Lin (ORCID: https://orcid.org/0000-0001-7039-1228)
Institutions
- The University of Tokyo (JP)
- Zhejiang University (CN)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2025-08-20
- DOI
- https://doi.org/10.1109/ted.2025.3597578
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Key Research and Development Program of China