Characterizing Capacitor Top Plate Bias for More Accurate Electromagnetic Simulations
As frequencies increase, the use of smaller value metal-insulator-metal (MIM) capacitors increases. For small capacitors, errors due to the bias (as fabricated to as drawn difference) of the top plate can cause significant errors. This bias is not correctly monitored with resistance based W (RLWB) monitors and can be made worse if the resistive based RLWB is used. We present a simple capacitive based technique that uses only two test capacitors to determine the value of the capacitive linewidth bias (CLWB) that is more appropriate for use electromagnetic (EM) simulation and provides consistency with typical MIM compact models.
Authors
- Leonard Hayden (ORCID: https://orcid.org/0009-0005-8576-7597)
- P.J. Zampardi (ORCID: https://orcid.org/0000-0003-1285-0056)
- Quinn Davenport
Institutions
- Tabor College (US)
- Qorvo (United States) (US)
- Silicon Labs (United States) (US)
Publication Details
- Journal
- IEEE Transactions on Semiconductor Manufacturing
- Published
- 2025-08-20
- DOI
- https://doi.org/10.1109/tsm.2025.3600905
- Citations
- 2
- Primary Topic
- Electromagnetic Compatibility and Noise Suppression
- Type
- article
- Field-Weighted Citation Impact
- 1.46