On the SCA Resistance of TMR-Protected Cryptographic Designs

The influence of redundant implementations on success of physical attacks against cryptographic devices is currently under-researched. This is especially an issue in application fields such as wearable health, industrial control systems and the like in which devices are accessible to potential attackers. This paper presents results of an investigation of the TMR application impact on the vulnerability of FPGA-based asymmetric cryptographic accelerators to side-channel analysis attacks. We implemented our cryptographic cores using full- and partial-TMR application approaches and experimentally conducted evaluation of their side-channel resistance. Our results reveal that TMR can significantly impact side-channel leakage, either increasing resistance by introducing noise or amplifying leakage depending on the part of the design where redundancy was applied.