Test-Path Scheduling for Interposer-Based 2.5D Integrated Circuits Using an Orthogonal Learning-Based Differential Evolution Algorithm

2.5D integrated circuits (ICs), which utilize an interposer to stack multiple dies side by side, represent a promising architecture for improving system performance, integration density, and design flexibility. However, the complex interconnect structures present significant challenges for post-fabrication testing, especially when scheduling test paths under constrained test access mechanisms. This paper addresses the test-path scheduling problem in interposer-based 2.5D ICs, aiming to minimize both total test time and cumulative inter-die interconnect length. We propose an efficient orthogonal learning-based differential evolution algorithm, named OLELS-DE. The algorithm combines the global optimization capability of differential evolution with an orthogonal learning-based search strategy and an elites local search strategy to enhance the convergence and solution quality. Comprehensive experiments are conducted on a set of benchmark instances with varying die counts, and the proposed method is compared against five state-of-the-art metaheuristic algorithms and CPLEX. Experimental results demonstrate that OLELS-DE consistently outperforms the competitors in terms of test cost reduction and convergence reliability, confirming its robustness and effectiveness for complex test scheduling in 2.5D ICs.

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Publication Details

Journal
Mathematics
Published
2025-08-20
DOI
https://doi.org/10.3390/math13162679
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.00

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article

Test-Path Scheduling for Interposer-Based 2.5D Integrated Circuits Using an Orthogonal Learning-Based Differential Evolution Algorithm

Liyan Qiao, Libao Deng, Lili Zhang, Chunlei Li et al.
Mathematics
VLSI and Analog Circuit Testing
article

Test-Path Scheduling for Interposer-Based 2.5D Integrated Circuits Using an Orthogonal Learning-Based Differential Evolution Algorithm

Liyan Qiao, Libao Deng, Lili Zhang, Chunlei Li, Chu Chen, Guanyu Yuan
article en

Abstract

2.5D integrated circuits (ICs), which utilize an interposer to stack multiple dies side by side, represent a promising architecture for improving system performance, integration density, and design flexibility. However, the complex interconnect structures present significant challenges for post-fabrication testing, especially when scheduling test paths under constrained test access mechanisms. This paper addresses the test-path scheduling problem in interposer-based 2.5D ICs, aiming to minimize both total test time and cumulative inter-die interconnect length. We propose an efficient orthogonal learning-based differential evolution algorithm, named OLELS-DE. The algorithm combines the global optimization capability of differential evolution with an orthogonal learning-based search strategy and an elites local search strategy to enhance the convergence and solution quality. Comprehensive experiments are conducted on a set of benchmark instances with varying die counts, and the proposed method is compared against five state-of-the-art metaheuristic algorithms and CPLEX. Experimental results demonstrate that OLELS-DE consistently outperforms the competitors in terms of test cost reduction and convergence reliability, confirming its robustness and effectiveness for complex test scheduling in 2.5D ICs.

MathematicsVol. 13(16)
Harbin Institute of Technology (CN), Dublin City University (IE)
National Natural Science Foundation of China, Natural Science Foundation of Shandong Province, National Key Research and Development Program of China
Openalex Percentile: Top 77%
VLSI and Analog Circuit Testing
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Test-Path Scheduling for Interposer-Based 2.5D Integrated Circuits Using an Orthogonal Learning-Based Differential Evolution Algorithm — Liyan Qiao, Libao Deng, et al. · Mathematics (2025) | TGRS Research Map | TGRS