An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving −251.9 dB FOM <sub>Jitter-N</sub>
This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {FOM}_{\text {Jitter-N}}$</tex-math> </inline-formula> of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.5~{\mu }$</tex-math> </inline-formula>s to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6~{\mu }$</tex-math> </inline-formula>s using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.
Authors
- Sirou Li
- Kaiyun Cao
- C.‐J. Richard Shi (ORCID: https://orcid.org/0000-0002-3157-3464)
- Heyu Ren (ORCID: https://orcid.org/0000-0003-3386-2646)
- Liangjian Lyu (ORCID: https://orcid.org/0000-0002-6157-0109)
- Rongjin Xu (ORCID: https://orcid.org/0000-0003-0632-2775)
- Weijia Zeng
- Xing Wu
Institutions
- University of Washington (US)
- Shanghai Fudan Microelectronics (China) (CN)
- East China Normal University (CN)
Publication Details
- Journal
- IEEE Transactions on Circuits and Systems I Regular Papers
- Published
- 2025-08-20
- DOI
- https://doi.org/10.1109/tcsi.2025.3598334
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- Science and Technology Commission of Shanghai Municipality