A Network Architecture for Chiplet Interconnection Based on Small World Theory
A wafer-level reconfigurable optical interconnect architecture using small-world theory reduces path length via long-range optimization. At 64-node scale, it shows at least <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$40 \% / 21 \%$</tex> lower latency than Mesh/Torus and improves distributed ML efficiency through topology adaptation.
Authors
- Xiyang Lan
- Libin Wang (ORCID: https://orcid.org/0000-0002-7861-1560)
Institutions
- Beijing University of Posts and Telecommunications (CN)
Publication Details
- Published
- 2025-06-29
- DOI
- https://doi.org/10.23919/oecc/psc62146.2025.11110471
- Primary Topic
- Interconnection Networks and Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00