Optimized Memory Reliability Solutions for AI-Driven Automation Systems

As modern System-on-Chip (SoC) designs become increasingly complex, ensuring the reliability of embedded Static Random-Access Memory (SRAM) is a critical challenge, particularly in AI-driven robotics and automation systems. This study proposes an optimized RTL-BIST (Built-In Self-Test) IP Core, developed using High-Level Synthesis (HLS) techniques, to enhance the efficiency and effectiveness of embedded memory testing. The proposed IP core integrates an improved March mSR+ algorithm, significantly increasing fault coverage-particularly for Destructive Read/Write Coupling Faults (CFdrd)-achieving 100 % detection capability. Implemented and validated on an FPGA platform, the RTL-BIST IP core demonstrates superior fault detection and repair mechanisms, while minimizing power consumption and hardware overhead. Experimental results confirm that March mSR+ achieves the highest fault coverage (88.89 %) among tested algorithms, while maintaining the lowest total power dissipation (125.38 mW). These findings validate the proposed IP core as a high-performance, low-power, and scalable solution for embedded memory reliability in advanced semiconductor, AI-powered robotics, and automation applications. By ensuring robust memory testing, this study contributes to the development of highly reliable AI-driven robotic systems, where fault-tolerant embedded memory is essential for real-time decision-making and autonomous operations.