FPGA Implementation of Parallel Non-Integer Oversampling Timing Recovery with IQ Skew Compensation
A real-time timing recovery algorithm working under non-integer oversampling is proposed to reduce analog-to-digital converter (ADC) oversampling, which can obtain 2-dB optical signal-tonoise ratio (OSNR) gain from IQ skew compensation simultaneously.
Authors
- Ke Dong (ORCID: https://orcid.org/0000-0001-9801-0984)
- B. S. Zou (ORCID: https://orcid.org/0000-0002-1648-4965)
- Fan Li (ORCID: https://orcid.org/0000-0002-8771-8992)
- Wei Wang (ORCID: https://orcid.org/0000-0003-4281-9383)
Institutions
- Sun Yat-sen University (CN)
Publication Details
- Published
- 2025-06-29
- DOI
- https://doi.org/10.23919/oecc/psc62146.2025.11111629
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China
- Basic and Applied Basic Research Foundation of Guangdong Province