Design Optimization of Viterbi-Decoder Based Convolutional Codes on Reconfigurable Hardware

Convolutional code is widely used in satellite communication, mobile relay, digital television, and wireless local area networks. The Viterbi algorithm is mostly used to decode the convolutional coded sequence. This paper explores convolutional encoding and decoding and focuses on the important aspects of the Viterbi algorithm. In a reconfigurable device, resource utilization ensures efficient use of hardware resources, and power consumption in such devices is critical for energy efficiency. So, we proposed an architecture that significantly reduced resource allocation and provided less power consumption. The proposed approaches can be based on logic reduction and performance objectives.