A 3.5GHz 70dB SNDR Direct RF Sampling Time Interleaved Pipeline SAR-ADC with Capacitor Mismatch Calibration in CMOS 28nm

This paper presents the design of a dual channel 12-bit, 1GS/s Time Interleaved Analog to Digital Converter (TI-ADC) in 28nm CMOS technology for RF sampling. This ADC supports input tracking bandwidths of 3.5GHz for sub-sampling applications with an instantaneous bandwidth of 500MHz. Each channel consists of 10 pipeline stages to achieve 12-bit accuracy operating at 500MS/s. The 10 pipeline stages compose of 4-bit SAR ADC as a first stage with 1-bit redundancy, second stage onwards 1.5-bit ADC with 2X reference scaling and finally, 2-bit flash ADC. Unlike conventional architectures, the proposed pipeline ADC is a SHA less architecture using a conventional binary weighted Capacitive Digital to Analog Converter array (CDAC) for SAR-ADC and Multiplying Digital-to-Analog Converter (MDAC) to decrease the sampling mismatch between sub-ADC and MDAC. The dual channel TI-ADC uses the OTA sharing technique between two time interleaved channels to optimize power and chip area effectively. Further power reduction is achieved using 2X reference scaling technique in each channel. Channel level gain and capacitance mismatch calibration is implemented for first four stages and observed an improvement in SFDR and SINAD upto 30dB from simulations with a capacitor mismatch of ±20% and OTA dc gain of 55dB. Timing mismatch calibration is applied at interleaving level to decrease the sampling timing mismatch between the channels. The proposed dual channel TI-ADC operates at 1GS/s with power consumption of 170mW including reference buffers at 1V supply and achieves SINAD of 70 dB & SFDR of 74 dB at 3.4238 GHz of input frequency after calibration. This results in the FoM value of 62fJ/conv.