90dB Dynamic Range, Multi-Channel Data Acquisition ASIC for SONAR Application

The data acquisition & processing system is an important part of the sonar signal measurement system. This paper presents a stable, low noise, high performance (in-terms of noise & gain), multi-channel underwater acoustic signal conditioning system realized on an ASIC. The signal conditioning circuit having OTA with Class-AB output stage to drive the low impedance load, chopper-based stabilization, temperature independent OTA biasing scheme for SDM ADC, on-chip calibration & BIST setup are some of the innovative features incorporated in this IC. The ASIC is designed in 180nm CMOS process having all essential features of SONAR platforms using Cadence suit. Simultaneous acquisition of multi-channel analog signals (10uV-50mV) and accurate digital conversion circuits are realized and integrated on the chip. The data acquisition ASIC (8-channels) consists of low noise chopper-based frontend amplifier (noise ∼ 75nV i.e.-142dB) followed by signal conditioning chain and a 24-bit sigma delta ADC (SNDR ∼ 90dB). The ASIC occupies 8.5 × 8.5 sq.mm area and consumes 125mW/channel of power.

Authors

Institutions

Publication Details

Published
2025-03-06
DOI
https://doi.org/10.1109/icort64008.2025.11115174
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

90dB Dynamic Range, Multi-Channel Data Acquisition ASIC for SONAR Application

P. S. Sushma, Sushant Gaurav, D. Shravan Kumar, C. Sharada et al.
1 links
Analog and Mixed-Signal Circuit Design
article

90dB Dynamic Range, Multi-Channel Data Acquisition ASIC for SONAR Application

P. S. Sushma, Sushant Gaurav, D. Shravan Kumar, C. Sharada, Kiran Kumar Garje
article en

Abstract

The data acquisition & processing system is an important part of the sonar signal measurement system. This paper presents a stable, low noise, high performance (in-terms of noise & gain), multi-channel underwater acoustic signal conditioning system realized on an ASIC. The signal conditioning circuit having OTA with Class-AB output stage to drive the low impedance load, chopper-based stabilization, temperature independent OTA biasing scheme for SDM ADC, on-chip calibration & BIST setup are some of the innovative features incorporated in this IC. The ASIC is designed in 180nm CMOS process having all essential features of SONAR platforms using Cadence suit. Simultaneous acquisition of multi-channel analog signals (10uV-50mV) and accurate digital conversion circuits are realized and integrated on the chip. The data acquisition ASIC (8-channels) consists of low noise chopper-based frontend amplifier (noise ∼ 75nV i.e.-142dB) followed by signal conditioning chain and a 24-bit sigma delta ADC (SNDR ∼ 90dB). The ASIC occupies 8.5 × 8.5 sq.mm area and consumes 125mW/channel of power.

Defence Research and Development Organisation (IN)
Affordable and clean energy
Openalex Percentile: Top 80%
Analog and Mixed-Signal Circuit Design
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.